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INTEGRATED CIRCUITS
DATA SHEET
TSA5526; TSA5527 1.3 GHz universal bus-controlled TV synthesizers
Product specification Supersedes data of 1995 Mar 22 File under Integrated Circuits, IC02 1996 Sep 24
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled TV synthesizers
FEATURES * Complete 1.3 GHz single chip system * Four PNP band switch buffers (40 mA) * 33 V output tuning voltage * In-lock detector * 5-step ADC * 15-bit programmable divider * Programmable reference divider ratio (512, 640 or 1024) * Programmable charge-pump current (60 or 280 A) * Programmable automatic charge-pump current switch * Varicap drive disable * Universal bus protocol I2C-bus or 3-wire bus: - bus protocol for 18 or 19 bits transmission (3-wire bus) - extra protocol for 27 bits for test and features (3-wire bus) - address plus 4 data bytes transmission (I2C-bus write mode) - address plus 1 status byte transmission (I2C-bus read mode) - three independent I2C-bus addresses * Low power and low radiation. ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TSA5526M TSA5526T TSA5527M TSA5527T TSA5526AM TSA5526AT TSA5527AM TSA5527AT SSOP16 SO16 SSOP16 SO16 SSOP16 SO16 SSOP16 SO16 DESCRIPTION APPLICATIONS
TSA5526; TSA5527
* TV tuners and front ends * VCR tuners.
VERSION SOT369-1 SOT109-1 SOT369-1 SOT109-1 SOT369-1 SOT109-1 SOT369-1 SOT109-1
plastic shrink small outline package; 16 leads; body width 4.4 mm plastic small outline package; 16 leads; body width 3.9 mm plastic shrink small outline package; 16 leads; body width 4.4 mm plastic small outline package; 16 leads; body width 3.9 mm plastic shrink small outline package; 16 leads; body width 4.4 mm plastic small outline package; 16 leads; body width 3.9 mm plastic shrink small outline package; 16 leads; body width 4.4 mm plastic small outline package; 16 leads; body width 3.9 mm
1996 Sep 24
2
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled TV synthesizers
QUICK REFERENCE DATA SYMBOL VCC1 VCC2 ICC1 ICC2 fRF Vi(RF) PARAMETER supply voltage (+5 V) band switch supply voltage (12 V) supply current band switch supply current RF input frequency RF input voltage fi = 80 to 150 MHz fi = 150 to 1000 MHz fi = 1000 to 1300 MHz fxtal Io(PNP) Ptot Tstg Tamb Notes 1. One band switch buffer ON, Io = 40 mA. crystal oscillator input frequency PNP band switch buffers output current total power dissipation storage temperature operating ambient temperature note 2 note 3 note 1 CONDITIONS MIN. 4.5 VCC1 - - 64 -25 -28 -15 3.2 4 - -40 -20
TSA5526; TSA5527
TYP. - 12 20 50 - - - - 4.0 - 250 - -
MAX. 5.5 13.5 25 55 1300 3 3 3 4.48 50 400 +150 +85 V V
UNIT
mA mA MHz dBm dBm dBm MHz mA mW C C
2. One band switch buffer ON, Io = 40 mA; two buffers ON, maximum sum of Io = 50 mA. 3. The power dissipation is calculated as follows: P D = V CC1 x I CC1 + V CC2 x ( I CC2 - I o ) + I o x V CE ( satPNP ) + ( V33 2 ) 27 k.
2
1996 Sep 24
3
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled TV synthesizers
GENERAL DESCRIPTION The device is a single-chip PLL frequency synthesizer designed for TV and VCR tuning systems. The circuit consists of a divide-by-eight prescaler with its own preamplifier, a 15-bit programmable divider, a crystal oscillator and its programmable reference divider and a phase/frequency detector combined with a charge-pump which drives the tuning amplifier and the 33 V output. Four high-current PNP band switch buffers are provided for band switching. Two PNP buffers can be switched on simultaneously. The sum of the collector currents is limited to 50 mA. Depending on the reference divider ratio (512, 640 or 1024), the phase comparator operates at 3.90625 kHz, 6.25 kHz or 7.8125 kHz using a 4 MHz crystal. The device can be controlled in accordance with the I2C-bus format or the 3-wire bus format depending on the voltage applied to the SW input (see Table 2). In the 3-wire bus mode (SW = HIGH) pin 12 is the LOCK output. The lock output is LOW when the PLL loop is locked. In the I2C-bus mode (SW = LOW) the LOCK detector bit FL is set to logic 1 when the loop is locked and is read on the SDA line (status byte) during a read operation. The ADC input is available on pin 12 for AFC control in the I2C-bus mode only. The ADC code is read during a read operation on the I2C-bus. In the test mode pin 12 is used as a test output for fref and 12fdiv in the I2C-bus mode and the 3-wire bus mode (see Table 6). When the automatic charge-pump current switch mode is activated, depending on the device given in Table 6, and when the loop is phase-locked, the charge-pump current value is automatically switched to LOW. Table 1 Differences between TSA5526 and TSA5527 DATA WORD 18-bit 19-bit 19-bit
TSA5526; TSA5527
This action is taken to improve the carrier-to-noise ratio. The status of this feature can be read in the ACPS flag during a read operation on the I2C-bus (see Table 8). I2C-bus format (SW = LOW) Five serial bytes (including address byte) are required to address the device, select the VCO frequency, program the four PNP band switch buffers, set the charge-pump current and the reference divider ratio. The device has three independent I2C-bus addresses which can be selected by applying a specific voltage on the CE input (see Table 5). The general address C2 is always valid. When the I2C-bus format is fully used, TSA5526 and TSA5527 are equal. 3-wire bus format (SW = VCC1 or open-circuit) Data is transmitted to the device during a HIGH level on the CE input (enable line pin 15). The device is compatible with 18-bit and 19-bit data formats. The first four bits are used to program the PNP band switch buffers and the remaining bits are used to control the programmable divider. A 27-bit data format may also be used to set the charge-pump current, the reference divider ratio and for test purposes. The differences between TSA5526 and TSA5527 are given in Table 1. When the 27-bit format is used, the TSA5526 and TSA5527 are equal and the reference divider is controlled by the RSA and RSB bits (see Table 7 and Figs 3, 4 and 5).
TYPE NUMBER TSA5526 TSA5526 TSA5527 Notes
REFERENCE DIVIDER 512(1) 1024(1) 640(2)
FREQUENCY STEP (kHz) 62.5 31.25 50
1. The selection of the reference divider is given by an automatic identification of the data word length. 2. The reference divider is set to 640 at power-on reset.
1996 Sep 24
4
1996 Sep 24
9 CP V tune 10 f div DIVIDER 512/640/1024 f ref CP RSA RSB T2,T1,T0 15-BIT FREQUENCY REGISTER IN-LOCK DETECTOR LOGIC lock RSA,RSB 3 OS 4-BIT BAND SWITCH REGISTER GATE 7-BIT CONTROL REGISTER 2 VCC1 VEE
AMP
BLOCK DIAGRAM
Philips Semiconductors
handbook, full pagewidth
RF
1 PRESCALER DIVIDE-BY-8 CHARGE PUMP
15-BIT PROGRAMMABLE DIVIDER
16
XTAL
XTAL OSCILLATOR
DIGITAL PHASE COMPARATOR
1.3 GHz universal bus-controlled TV synthesizers
POWER-ON RESET
13
SCL
14
5
T2,T1,T0 4 VCC2 BS1 BS2 BS3 BS4 8 7 6 5
SDA
15
I 2 C/3-WIRE BUS TRANSCEIVER
CE
SW
11
5-LEVEL ADC
12
TSA5526 TSA5527
MBE327
LOCK/ ADC
TSA5526; TSA5527
Product specification
Fig.1 Block diagram.
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled TV synthesizers
PINNING SYMBOL RF VEE VCC1 VCC2 BS4 BS3 BS2 BS1 CP Vtune SW LOCK/ADC SCL SDA CE XTAL PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ground supply voltage (+5 V) band switch supply voltage (+12 V) PNP band switch buffer output 4 PNP band switch buffer output 3 PNP band switch buffer output 2 PNP band switch buffer output 1 charge-pump output tuning voltage output bus format selection input, I2C-bus or 3-wire lock detector output (3-wire bus/ ADC input (I2C-bus) serial clock input serial data input/output chip enable/address selection input crystal oscillator input
handbook, halfpage
TSA5526; TSA5527
DESCRIPTION RF signal input
RF VEE V CC1 VCC2 BS4 BS3 BS2 BS1
1 2 3 4 5 6 7 8
MBE326
16 XTAL 15 CE 14 SDA
TSA5526 TSA5527
13 SCL 12 LOCK/ADC 11 SW 10 V tune 9 CP
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION The device is controlled via the I2C-bus or the 3-wire bus depending on the voltage applied to the SW input (pin 11). A HIGH level on the SW input enables the 3-wire bus inputs which are CE (Chip Enable), SDA (serial data input) and SCL (serial clock input). A LOW level on the SW input enables the I2C-bus inputs which are AS (Address Selection input), SDA (serial data input/output) and SCL (serial clock input). The bus format selection is given in Table 2. I2C-bus mode (SW = LOW); see Table 3 WRITE MODE (R/W = 0) Data bytes can be sent to the device after the address transmission (first byte). Four data bytes are required to fully program the device. The bus transceiver has an auto-increment facility which permits the programming of the device within one single transmission (address + 4 data bytes). The device can also be partially programmed providing that the first data byte following the address is Divider Byte 1 (DB1) or the Control Byte (CB). The bits in the data bytes are defined in Table 3.
The first bit of the first data byte transmitted indicates whether frequency data (first bit = logic 0) or control and band switch data (first bit = logic 1) will follow. Until an I2C-bus STOP command is sent by the controller, additional data bytes can be entered without the need to readdress the device. The frequency register is loaded after the 8th clock pulse of the second Divider Byte (DB2), the control register is loaded after the 8th clock pulse of the Control Byte (CB) and the band switch register is loaded after the 8th clock pulse of the Band switch Byte (BB). I2C-BUS ADDRESS SELECTION The module address contains programmable address bits (MA1 and MA0) which offer the possibility of having several synthesizers (up to 3) in one system by applying a specific voltage to the CE input. The relationship between MA1 and MA0 and the input voltage applied to the CE input is given in Table 5.
1996 Sep 24
6
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled TV synthesizers
Table 2 Bus format selection PIN 11 12 13 14 15 Table 3 I2C-bus data format BYTE Address Byte (ADB) Divider Byte 1 (DB1) Divider Byte 2 (DB2) Control Byte (CB) Band switch Byte (BB) Table 4 MSB 1 0 N7 1 X 1 N14 N6 CP X 0 N13 N5 T2 X DATA BYTE 0 N12 N4 T1 X 0 N11 N3 T0 BS4 MA1 N10 N2 RSA BS3 NAME SW LOCK/ADC SCL SDA CE 3-WIRE BUS MODE OPEN or HIGH LOCK/TEST output clock input data input chip enable input
TSA5526; TSA5527
I2C-BUS MODE LOW ADC input/TEST output SCL input SDA input/output address selection input
LSB MA0 N9 N1 RSB BS2 R/W = 0 N8 N0 OS BS1
SLAVE ANSWER A A A A A
Description of Table 3 SYMBOL DESCRIPTION acknowledge programmable address bits (see Table 5) programmable divider bits; N = N14 x 214 + N13 x 213 + ... + N1 x 2 + N0 charge-pump current; CP = 0 = 60 A; CP = 1 = 280 A (default) test bits (see Table 6); for normal operation T2 = 0, T1 = 0 and T0 = 1 (default) reference divider ratio select bits (see Table 7) tuning amplifier control bit; for normal operation OS = 0 and tuning voltage is ON (default); when OS = 1 tuning voltage is OFF (high impedance) PNP band switch buffers control bits; when BSn = 0 buffer n is OFF; when BSn = 1 buffer n is ON don't care I2C-bus address selection VOLTAGE APPLIED TO THE CE INPUT (SW = LOW) MA1 0 0 1 1 MA0 0 1 0 1
A MA1 and MA0 N14 to N0 CP T2 to T0 RSA and RSB OS BS4 to BS1 X Table 5
0 V to 0.1VCC1 Always valid 0.4VCC1 to 0.6VCC1 0.9VCC1 to VCC1
1996 Sep 24
7
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled TV synthesizers
Table 6 T2 0 0 0 1 1 1 1 T1 0 0 1 1 1 0 0 Test bits T0 0 1 X 0 1 0 1 TSA5526; TSA5527 normal operation with automatic charge-pump switch ON normal operation with automatic charge-pump switch OFF charge-pump is OFF charge-pump is sinking current charge-pump is sourcing current fref is available at LOCK output
1 2fdiv
TSA5526; TSA5527
TSA5526A; TSA5527A automatic charge-pump switch OFF automatic charge-pump switch ON charge-pump is OFF charge-pump is sinking current charge-pump is sourcing current fref is available at LOCK output
1 2fdiv
REMARKS
status at POR
the ADC cannot be used when test mode is active the ADC cannot be used when test mode is active
is available at LOCK output
is available at LOCK output
Table 7
Ratio select bits RSB 0 1 1 REFERENCE DIVIDER 640 1024 512
RSA X 0 1
The device will then release the data line to allow the microcontroller to generate a stop condition. The POR flag is set to logic 1 at power-on. The flag is reset when an end-of-data is detected by the device (end of a read sequence). Control of the loop is made possible with the in-lock flag (FL) which indicates when the loop is locked (FL = logic 1). The Automatic Charge-Pump Switch flag (ACPS) is LOW when the automatic charge-pump switch mode is ON and the loop is locked. In other conditions ACPS = logic 1. When ACPS = logic 0, the charge-pump current is forced to the LOW value. A built-in ADC is available at pin 12 (I2C-bus only). This converter can be used to apply AFC information to the microcontroller from the IF section of the television. The relationship between the bits A2 to A0 is given in Table 9.
READ MODE (R/W = LOGIC 1); see Table 8 Data can be read from the device by setting the R/W bit to logic 1. After the slave address has been recognized, the device generates an acknowledge pulse and the first data byte (status byte) is transferred on the SDA line (MSB first). Data is valid on the SDA line during a HIGH level of the SCL clock signal. A second data byte can be read from the device if the microcontroller generates an acknowledge on the SDA line (master acknowledge). End of transmission will occur if no master acknowledge occurs. Table 8 Read data format BYTE Address Byte (ADB) Status Byte (SB) Notes 1. A = acknowledge. 2. POR = power-on reset flag (POR = logic 1 at power-on). 3. FL = in-lock flag (FL = logic 1 when the loop is locked). MSB 1 POR(2) 1 FL(3) 0 ACPS(4)
DATA BYTE 0 1 0 1 MA1 A2(5) MA0 A1(5)
LSB R/W = 1 A0(5)
SLAVE ANSWER A(1) -
4. ACPS = automatic charge-pump switch flag (active ACPS = logic 0; non-active ACPS = logic 1). 5. A2 to A0 = digital outputs of the 5-level ADC.
1996 Sep 24
8
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled TV synthesizers
Table 9 ADC levels A2 1 0 0 0 0 A1 0 1 1 0 0 A0 0 1 0 1 0
TSA5526; TSA5527
application; see Fig.12), the test bits T2, T1 and T0 are set to the 0 0 1 state in the normal mode with ACPS OFF for TSA55226; TSA5527 and ACPS ON for TSA5526A; TSA5527A. RSB is set to logic 1 (TSA5526) or logic 0 (TSA5527). When an 18-bit data word is transmitted, the most significant bit of the divider N14 is internally set to logic 0 and bit RSA is set to logic 1. When a 19-bit data word is transmitted, bit RSA is set to logic 0. When a 27-bit word is transmitted, the frequency bits are loaded into the frequency register on the 20th rising edge of the clock pulse and the control bits at the HIGH-to-LOW transition of the chip enable line. In this mode, the reference divider is given by the RSA and RSB bits (see Table 7). The test bits T2, T1 and T0, the charge-pump bit CP, the ratio select bit RSB and the OS bit can only be selected or changed with a 27-bit transmission. They remain programmed if an 18-bit or a 19-bit transmission occurs. Only RSA is controlled by the transmission length when the 18-bit or 19-bit format is used. A data word of less than 18 bits will not affect the frequency register of the device. The definition of the bits is unchanged compared to the I2C-bus mode. The power-on detection threshold voltage VPOR is fixed to VCC1 = 2 V at room temperature. Below this threshold, the device is reset to the power-on state previously described.
VOLTAGE APPLIED AT ADC INPUT(1) 0.6VCC1 to VCC1 0.45VCC1 to 0.6VCC1 0.3VCC1 to 0.45VCC1 0.15VCC1 to 0.3VCC1 0 to 0.15VCC1 Note 1. Accuracy is 0.03VCC1.
3-wire bus mode (SW = open-circuit or VCC1); see Figs 3, 4 and 5 During a HIGH level on the CE input, the data is clocked into the data register at the HIGH-to-LOW transition of the clock pulse. The first four bits control the band switch buffers and are loaded into the internal band switch register on the 5th rising edge of the clock pulse. The frequency bits are loaded into the frequency register at the HIGH-to-LOW transition of the chip enable line when an 18-bit or 19-bit data word is transmitted. At power-on the charge-pump current is set to 280 A, the tuning voltage output is disabled (Vtune = 33 V in
For TSA5526 bit RSB = logic 1 at power-on; the reference divider is 512 or 1024. For TSA5527 bit RSB = logic 0 at power-on; the reference divider is 640. For TSA5526 and TSA5527 the value of RSB can also be programmed by using the 27-bit data format. When returning to the normal mode, bit RSB remains as programmed with the 27-bit data word.
Fig.3 Normal mode; 18-bit data format (RSA = 1).
1996 Sep 24
9
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled TV synthesizers
TSA5526; TSA5527
For TSA5526 bit RSB = 1 at power-on; the reference divider is 512 or 1024. For TSA5527 bit RSB = 0 at power-on; the reference divider is 640. For TSA5526/TSA5527 the value of RSB can also be programmed by using the 27-bit data format. When returning to the normal mode, bit RSB remains as programmed with the 27-bit data word.
Fig.4 Normal mode; 19-bit data format (RSA = 0).
For TSA5526 bit RSB = 1 at power-on; the reference divider is 512 or 1024. For TSA5527 bit RSB = 0 at power-on; the reference divider is 640. For TSA5526/TSA5527 the value of RSB can also be programmed by using the 27-bit data format. When returning to the normal mode, bit RSB remains as programmed with the 27-bit data word.
Fig.5 Test and features mode; 27-bit data format.
1996 Sep 24
10
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled TV synthesizers
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VCC1 VCC2 Vi(RF) Vo(BSn) Io(BSn) Vo(CP) Vo(tune) Vi(SW) Vo(LOCK) Vi(SCL) Vi/o(SDA) Io(SDA) Vi(CE) Vi(xtal) Tstg Tj tsc Note supply voltage; +5 V (pin 3) band switch supply voltage; +12 V (pin 4) prescaler input voltage (pin 1) band switch buffers output voltage (pins 5 to 8) band switch buffers output current charge-pump output voltage (pin 9) output tuning voltage (pin 10) input switching voltage (pin 11) lock output voltage (pin 12) serial clock input voltage (pin 13) serial data input/output voltage (pin 14) serial data output current chip enable input voltage (pin 15) crystal oscillator input voltage (pin 16) storage temperature maximum junction temperature PARAMETER
TSA5526; TSA5527
MIN. -0.3 -0.3 -0.3 -0.3 -1 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -1 -0.3 -0.3 -40 -
MAX. +6.0 +16 VCC1 VCC2 +50 VCC1 +35 VCC1 VCC1 +6.0 +6.0 +10 +6.0 VCC1 +150 +150 10
UNIT V V V V mA V V V V V V mA V V C C s
short-circuit time; every pin except pin 4 to pin 3 and every pin to pin 2; note 1 -
1. Short-circuit between VCC1 and VCC2 is allowed provided the voltage applied to VCC2 is less than the 6 V maximum rating at VCC1. THERMAL CHARACTERISTICS SYMBOL Rth j-a SO16 SSOP16 HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling bipolar devices. Every pin withstands the ESD test in accordance with "MIL-STD-883C" category B (2000 V). Every pin withstands the ESD test in accordance with Philips Semiconductors Machine Model 0 , 200 pF (200 V). PARAMETER thermal resistance from junction to ambient in free air 110 142 K/W K/W VALUE UNIT
1996 Sep 24
11
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled TV synthesizers
TSA5526; TSA5527
CHARACTERISTICS VCC1 = 4.5 to 5.5 V; VCC2 = VCC1 to 13.2 V; Tamb = -20 to +85 C; unless otherwise specified. SYMBOL Supplies VCC1 VCC2 ICC1 ICC2 supply voltage band switch buffers supply voltage supply current band switch buffers supply current at power-on at power-on one band switch buffer is ON; Isource = 40 mA 4.5 VCC1 - - - - - 20 0.5 50 56 5.5 13.5 25 1.0 55 62 V V mA mA mA mA PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
two band switch buffers are - ON; Isource = 40 mA + 5 mA (any combination) VPOR fRF DR fxtal Zxtal supply voltage below which POR is active RF input frequency divider ratio crystal oscillator input frequency crystal oscillator input impedance (absolute value) 15-bit frequency word 14-bit frequency word Rxtal = 25 to 300 fi = 4 MHz 1.5 64 256 256 3.2 600
2.0 - - - 4 1 200
- 1300 32767 16383 4.48 -
V MHz
MHz
Prescaler (see Figs 6 and 7) Vi(RF) RF input level fi = 80 to 150 MHz fi = 150 to 1000 MHz fi = 1000 to 1300 MHz Zi(RF) ILO Vo(sat) input impedance see Fig.8 -10 - - 0.2 - 0.4 A V PNP band switch buffers outputs (pins 5 to 8) output leakage current output saturation voltage VCC2 = 13.5 V; Vo = 0 V Isource = 40 mA; Vo(sat) = VCC2 - Vo VCC1 = 5.5 V; Vo = 5.5 V Isource = 200 A; Vo(sat) = VCC1 - Vo -25 -28 -15 - - - 3 3 3 dBm dBm dBm
LOCK output (PNP collector output) 3 wire bus mode (pin 12) Io(ool) Vosat(ool) Vo(LOCK) output current when out-of-lock output saturation voltage when out-of-lock lock output voltage - - - - 0.4 0.01 - - - 100 0.8 0.4 A V V
ADC input (I2C-bus mode) pin 12 Vi(ADC) IIH(ADC) IIL(ADC) ADC input voltage HIGH level input current LOW level input current see Table 9 VADC = VCC1 VADC = 0 V 0 - -10 VCC1 10 - V A A
1996 Sep 24
12
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled TV synthesizers
SYMBOL PARAMETER CONDITIONS
TSA5526; TSA5527
MIN. - - - - - - - - - - - - - -
TYP.
MAX.
UNIT
SW input (bus format switch) VIL VIH IIH IIL VIL VIH IIH IIL VIL VIH IIH IIL fclk LOW level input voltage HIGH level input voltage HIGH level input current LOW level input current VSW = VCC1 VSW = 0 V 0 3 - -100 1.5 VCC1 10 - V V A A
CE input (chip enable/address selection) LOW level input voltage HIGH level input voltage HIGH level input current LOW level input current VCE = 5.5 V VCE = 0 V 0 3 - -10 1.5 5.5 10 - V V A A
SCL and SDA inputs LOW level input voltage HIGH level input voltage HIGH level input current LOW level input current clock frequency (I2C-bus mode) VSDA = 5.5 V Isink = 3 mA CP = 1 CP = 0 in-lock; Tamb = 25 C T2 = 0; T1 = 1 - - - - - -15 - 0.2 - - 10 0.4 - - - +15 A V A A V nA A V VBUS = 5.5 V; VCC1 = 0 V VBUS = 5.5 V; VCC1 = 5.5 V VBUS = 1.5 V; VCC1 = 0 V VBUS = 0 V; VCC1 = 5.5 V SDA outputs ILO Vo |IICPH| |IICPL| VCP ILI(off) 0 3.0 - - - -10 - 1.5 5.5 10 10 10 - 400 V V A A A A kHz
100
output leakage current output voltage
Charge-pump output CP HIGH charge-pump current LOW charge-pump current output voltage off-state leakage current 280 60 1.95 -0.5 - -
Tuning voltage output Vtune ILO(off) Vo leakage current when switched-off output voltage when the loop is closed OS = 1; Vtune = 33 V OS = 0; T2 = 0; T1 = 0; T0 = 1; RL = 27 k; Vtune = 33 V 10 32.7
3-wire bus timing (see Figs 6 and 7) tHIGH tSU;DAT tHD;DAT tSU;ENSCL tHD;ENDAT tEN tHD;ENSCL 1996 Sep 24 clock high time data set-up time data hold time enable to clock set-up time enable to data hold time enable between two transmissions enable to clock active edge hold time 13 2 2 2 10 2 10 6 - - - - - - - - - - - - - - s s s s s s s
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled TV synthesizers
TSA5526; TSA5527
Fig.6 Timing diagram for 3-wire bus; SDA, SCL and CE.
Fig.7 Timing diagram for 3-wire bus; CE and SCL.
1996 Sep 24
14
BBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBBB
Fig.8 Prescaler Smith chart of typical input impedance at pin 1. Fig.9 Prescaler typical input sensitivity curve.
1996 Sep 24 Philips Semiconductors
1.3 GHz universal bus-controlled TV synthesizers
15
TSA5526; TSA5527
Product specification
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled TV synthesizers
INTERNAL PIN CONFIGURATION
handbook, full pagewidth
VCC1
TSA5526; TSA5527
internal Vref reference voltage
VCC1
RF
1 16 XTAL
VEE V EE VCC1 VCC2 2
VEE VCC1
3
15 CE
4 to address selection VEE VCC1
VCC2
BS4
5
14 SDA
ACK VEE VCC2 (I2 C BUS)
VEE VCC1
13
6 BS3
TSA5526 TSA5527
VEE VCC1 command 12
SCL
LOCK/ADC VEE VCC2 VEE VCC1
BS2
7
11 SW VEE 10 VEE V tune
VCC2 VEE VCC1 down 9 CP
8 BS1
VEE
up
VEE
MGD635
Fig.10 Internal pin configuration.
1996 Sep 24
16
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled TV synthesizers
APPLICATION INFORMATION Tuning amplifier The tuning amplifier is capable of driving the varicap voltage without an external transistor. The tuning voltage output must be connected to an external load of 27 k which is connected to the tuning voltage supply rail. Figs 11 and 12 show a possible loop filter. The component values depend on the oscillator characteristics and the selected reference frequency. Examples of I2C-bus sequences (SW = LOW) Crystal oscillator
TSA5526; TSA5527
The crystal oscillator uses a 4 MHz crystal connected in series with an 18 pF capacitor thereby operating in the series resonance mode. Connecting the oscillator to the supply voltage is preferred but it can, however, also be connected to ground.
Tables 10 to 14 show the various sequences where fosc = 100 MHz, BS4 = ON, ICP = 280 A, N = 512, fxtal = 4 MHz, S = START, A = acknowledge and P = STOP. The sequence is as follows: START + address byte + divider byte 1 + divider byte 2 + control byte + band switch byte + STOP. For the complete sequence see Table 10 (sequence 1) or Table 11 (sequence 2). Table 10 Complete sequence 1 S C2 A 06 A 40 A CE A 08 A P
Table 11 Complete sequence 2 S C2 A CE A 08 A 06 A 40 A P
Table 12 Divider bytes only sequence S C2 A 06 A 40 A P
Table 13 Control and band switch bytes only sequence S C2 A CE A 08 A P
Table 14 Control byte only sequence S C2 A CE A P
Other sequences are not allowed in the write mode. Table 15 One status byte acquisition S Notes 1. XX = the read status byte. 2. X = no acknowledge from the master means end of sequence. C3 A XX(1) X(2) P
1996 Sep 24
17
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled TV synthesizers
Table 16 Two status byte acquisition S Notes 1. XX = the read status byte. 2. X = no acknowledge from the master means end of sequence. C3 A XX(1) A XX(1)
TSA5526; TSA5527
X(2)
P
Other I2C-bus addresses may be selected by applying an appropriate voltage to the CE input. Examples of 3-wire bus sequences (TSA5526; SW = OPEN) Table 17 18-bit sequence (fosc = 800 MHz, BS4 = ON) 1 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0
The reference divider is automatically set to 512 unless RSB has been programmed to 0 during a 27-bit sequence (see Table 19). Table 18 19-bit sequence (fosc = 650 MHz, BS3 = ON) 0 1 0 0 1 0 1 0 0 0 1 0 1 0 0 0 0 0 0
The reference divider is automatically set to 1024 unless RSB has been programmed to 0 during a 27-bit sequence (see Table 19). Table 19 27-bit sequence (fosc = 750 MHz, BS1 = ON, N = 640, Icp = 60 A, no test function) 0 0 0 1 0 1 1 1 0 1 0 1 0 0 1 1 0 0 0 1 0 0 0 1 0 0 0
Table 20 19-bit sequence 0 0 0 1 0 1 0 1 1 1 0 1 1 1 0 0 0 0 0
This sequence will program fosc to 600 MHz in 50 kHz steps. ICP remains at 60 A. Table 21 18-bit sequence 0 0 0 1 1 0 1 1 1 0 1 1 1 0 0 0 0 0
This sequence will program fosc to 600 MHz in 50 kHz steps. ICP remains at 60 A. Table 22 27-bit sequence (fosc = 650 MHz, BS1 = ON) 0 0 0 1 1 0 1 0 0 0 1 0 1 0 0 0 0 0 0 1 1 0 0 1 0 1 0
This sequence sets RSA to 0, RSB to 1 and CP to 1. After this sequence ICP = 280 A, N = 1024 (19-bit transmission) and N = 512 (18-bit transmission), RSB = 1.
1996 Sep 24
18
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled TV synthesizers
Example of 3-wire bus sequence (TSA5527; SW = OPEN) Table 23 19-bit sequence (fosc = 700 MHz, BS3 = ON) 0 1 0 0 0 1 1 0 1 1 0 1 0 1
TSA5526; TSA5527
1
0
0
0
0
N = 640 unless RSB has been programmed to 0 during a 27-bit sequence.
22 k
handbook, full pagewidth
2.2 nF 100 nF CP 22 k V tune SW LOCK SCL SDA AS LOCK SCL SDA CE XTAL BS2 BS3 BS4 VCC2 VCC1 V EE RF BS1
27 k 33 V SWITCH HIGH MID LOW 12 V
10 nF (2)
33 nF
V tune
TSA552X
RF 1 nF 5V
MLC887
4 MHz
18 pF
(1)
(1) Connection to ground is also allowed. (2) Capacitor prevents parasitic oscillation on the VCC2 line.
Fig.11 Typical I2C-bus application.
1996 Sep 24
19
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled TV synthesizers
TSA5526; TSA5527
handbook, full pagewidth
22 k 27 k 33 V 100 nF CP 22 k V tune SW LOCK CLOCK DATA ENABLE LOCK SCL SDA CE XTAL BS2 BS3 BS4 VCC2 VCC1 V EE RF 1 nF 5V
MLC888
33 nF
V tune
2.2 nF
BS1
SWITCH HIGH MID LOW 12 V
10 nF (2)
TSA552X
RF
4 MHz
18 pF
(1)
(1) Connection to ground is also allowed. (2) Capacitor prevents parasitic oscillation on the VCC2 line.
Fig.12 Typical 3-wire bus application.
1996 Sep 24
20
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled TV synthesizers
PACKAGE OUTLINES SO16: plastic small outline package; 16 leads; body width 3.9 mm
TSA5526; TSA5527
SOT109-1
D
E
A X
c y HE vMA
Z 16 9
Q A2 A1 pin 1 index Lp 1 e bp 8 wM L detail X (A 3) A
0
2.5 scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 1.75 0.069 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 10.0 9.8 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.050 HE 6.2 5.8 0.24 0.23 L 1.05 0.041 Lp 1.0 0.4 0.039 0.016 Q 0.7 0.6 0.028 0.020 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) 0.7 0.3 0.028 0.012
0.0098 0.057 0.0039 0.049
0.019 0.0098 0.39 0.014 0.0075 0.38
8 0o
o
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT109-1 REFERENCES IEC 076E07S JEDEC MS-012AC EIAJ EUROPEAN PROJECTION
ISSUE DATE 91-08-13 95-01-23
1996 Sep 24
21
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled TV synthesizers
TSA5526; TSA5527
SSOP16: plastic shrink small outline package; 16 leads; body width 4.4 mm
SOT369-1
D
E
A X
c y HE vM A
Z
16
9
Q A2 pin 1 index A1 (A 3) Lp L A
1
e bp
8
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.5 A1 0.15 0.00 A2 1.4 1.2 A3 0.25 bp 0.32 0.20 c 0.25 0.13 D (1) 5.30 5.10 E (1) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1.0 Lp 0.75 0.45 Q 0.65 0.45 v 0.2 w 0.13 y 0.1 Z (1) 0.48 0.18 10 0o
o
Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT369-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 94-04-20 95-02-04
1996 Sep 24
22
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled TV synthesizers
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Reflow soldering Reflow soldering techniques are suitable for all SO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. Wave soldering
TSA5526; TSA5527
Wave soldering techniques can be used for all SO packages if the following conditions are observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow. * The package footprint must incorporate solder thieves at the downstream end. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1996 Sep 24
23
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled TV synthesizers
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TSA5526; TSA5527
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1996 Sep 24
24
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled TV synthesizers
NOTES
TSA5526; TSA5527
1996 Sep 24
25
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled TV synthesizers
NOTES
TSA5526; TSA5527
1996 Sep 24
26
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled TV synthesizers
NOTES
TSA5526; TSA5527
1996 Sep 24
27
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1996
Internet: http://www.semiconductors.philips.com
SCA51
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
537021/50/02/pp28
Date of release: 1996 Sep 24
Document order number:
9397 750 01258

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